Patents

Gary Delp holds over 50 patents. Links connect to the patent details at the US Patent & Trademark Office.

7,496,861, Method for generalizing design attributes in a design capture environment,
filed: November 30, 2005, issued: February 24, 2009
Inventors: George W. Nation, Gary Lippert, Gary S. Delp
A method for generalizing design attributes in a design capture environment comprising the steps of (A) defining a procedure for adding one or more auxiliary configurators to a tool or suite of tools, (B) linking the auxiliary configurators to predetermined object points in an abstracted design and (C) defining a procedure for the tool or suite of tools to reference the one or more auxiliary configurators, wherein the auxiliary configurators are neither referenced by a core nor built into the tool or suite of tools.

7,491,579, Composable system-in-package integrated circuits and process of composing the same,
filed: March 14, 2005, issued: February 17, 2009
Inventors: Gary S. Delp, George Wayne Nation
An SIP for performing a plurality of hard and soft functions comprises standard IC die and custom platforms mounted to a substrate. Die are identified for each standard hard function, such as memory, processing, I/O and other standard functions and one or more user-configurable base platforms are selected that, when configured, execute the custom soft functions. Optionally, the substrate is laminated to the die and the platforms are attached to the substrate. Testing is performed by defining the configured base platforms coupled to logic representing the die and their connections and performing placement and timing closure on the combination.

7,430,725, Suite of tools to design integrated circuits,
filed: June 18, 2005, issued: September 30, 2008
Inventors: Broberg, Robert Neal Carlton III, Jonathan William Byrn, Gary Scott Delp, Michael K. Eneboe, Gary Paul McClannahan, George Wayne Nation, Paul Gary Reuland, Thomas Sandoval, Matthew Scott Wingren
A set of tools is provided herein that produces useful, proven, and correct integrated semiconductor chips. Having as input either a customer's requirements for a chip, or a design specification for a partially manufactured semiconductor chip, the tools generate the RTL for control plane interconnect; memory composition, test, and manufacture; embedded logic analysis, trace interconnection, and utilization of spare resources on the chip; I/O qualification, JTAG, boundary scan, and SSO analysis; testable clock generation, control, and distribution; interconnection of all of the shared logic in a testable manner from a transistor fabric and/or configurable blocks in the slice. The input customer requirements are first conditioned by RTL analysis tools to quickly implement its logic. The slice definition and the RTL shell provides the correct logic for a set of logic interfaces for the design specification to connect. The tools share a common database so that logical interactions do not require multiple entries. The designs are qualified, tested, and verified by other tools. The tools further optimize the placement and timing of the blocks on the chip with respect to each other and with respect to placement on a board. The suite may be run as batch processes or can be driven interactively through a common graphical user interface. The tools also have an iterative mode and a global mode. In the iterative mode, one or more of the selected tools can generate the blocks or modify a design incrementally and then look at the consequences of the addition, or change. In the global mode, the semiconductor product is designed all at once in a batch process as above and then optimized altogether. This suite of generation tools generates design views including a qualified netlist for a foundry to manufacture.

7,405,476, Asymmetric alignment of substrate interconnect to semiconductor die,
filed: October 27, 2005, issued: July 29, 2008
Inventors: Gary S. Delp
An apparatus includes a first semiconductor die and at least one further semiconductor die. A substrate is attached to the first die and the further die and has an electrical interconnect pattern that interconnects contacts on the first die with respective contacts on the further die. Features of the interconnect pattern have positions on the substrate with smaller tolerances relative to positions of the contacts on the first die than to positions of the contacts on the further die.

7,404,154, Basic cell architecture for structured application-specific integrated circuits,
filed: July 25, 2005, issued: July 22, 2008
Inventors: Ramnath Venkatraman, Michael N. Dillon, David A. Gardner, Monzel, Carl Anthony III, Subramanian Ramesh, Robert C. Armstrong, Gary Scott Delp, Scott Allen Peterson
A basic cell circuit architecture having plurality of cells with fixed transistors configurable for the formation of logic devices and/or single/dual port memory devices within a structured ASIC is provided. Different configurations of ensuing integrated circuits are achieved by forming variable interconnect layers above the fixed structures. The circuit architecture can achieve interconnection of transistors within a single cell and/or across multiple cells. The interconnection can be configured to form basic logic gates as well as more complex digital and analog subsystems. In addition, each cell contains a layout of transistors that can be variably coupled to achieve a memory device, such as a SRAM device. By having the capability of forming either a logic circuit element, a memory device, or both, the circuit architecture is both memory-centric and logic-centric, and more fully adaptable to modern-day SoCs.

7,352,748, Updating of routing data in a network element,
filed: November 12, 2002, issued: April 1, 2008
Inventors: Ranjit Rozario, Gary S. Delp
In one embodiment, an apparatus comprises a logic coupled to receive a number of data packets. The logic comprises an execution unit to generate a request for routing data for a data packet of the number of data packets. The logic also includes a memory lookup engine coupled to the execution unit and a local memory. The local memory is to store routing data for the number of data packets. The memory lookup engine is to receive the request and to update the local memory upon determining that the routing data for the data packet is not found in the local memory. Additionally, the logic includes a communication logic coupled to the memory lookup engine. The communication logic is to transmit an update message to a remote logic. The update message is to cause the remote logic to update a remote memory, wherein the update message is transmitted based on a low priority update upon determining that a buffer for update messages of the remote memory is full when the local memory is updated.

7,301,906, Methods and structures for improved buffer management and dynamic adaption of flow control status in high-speed communication networks,
filed: August 30, 2002, issued: November 27, 2007
Inventors: George Wayne Nation, Gurumani Senthil, Gary Scott Delp
Methods and structure for standardized, high-speed serial communication to reduce memory capacity requirements within receiving elements of a high-speed serial communication channel. In an exemplary SPI compliant embodiment of the invention, the semantic meaning of the STARVING, HUNGRY and SATISFIED flow control states is modified to allow the transmitting and receiving elements to manage buffer storage in a more efficient manner to thereby reduce memory capacity requirements while maintaining the integrity of flow control contracts and commitments. The methods and structure further provide for generation of storage metric information to dynamically update the flow control status information asynchronously with respect to data packet transmissions.

7,069,523, Automated selection and placement of memory during design of an integrated circuit,
filed: December 13, 2002, issued: June 27, 2006
Inventors: George Wayne Nation, Gary Scott Delp, Paul Gary Reuland
A tool for designing integrated circuits that optimizes the placement and timing of memory blocks within the circuit. Given a manufactured slice that has a number of blocks already diffused and logically integrated, the memory generation tool herein automatically considers the available diffused memory and the gate array of the slices to configure and optimize them into a customer's requirements for memory. The memory generation tool has a memory manager, a memory resource database, a memory resource selector, and a memory composer. Together these all interact to generate memories from the available memories within the memory resource database. The memory composer actually generates the RTL logic shells for the memories, and outputs the memory designs in Verilog, VHDL, or other tool synthesis language. Once a memory is created, it is tested. Upon successful testing, the memory manager updates the memory resource database to indicate the successfully tested memory is no longer available as a resource for the generation of further memories. A design integrator may review the memory designs output and further integrate the memory, its timing, testing, etc. with other blocks and functions of the integrated circuit.

7,055,113, Simplified process to design integrated circuits,
filed: December 31, 2002, issued: May 30, 2006
Inventors: Broberg, Robert Neal Carlton III, Jonathan William Byrn, Gary Scott Delp, Michael K. Eneboe, Gary Paul McClannahan, George Wayne Nation, Paul Gary Reuland, Thomas Sandoval, Matthew Scott Wingren
A set of tools is provided herein that produces useful, proven, and correct integrated semiconductor chips. Having as input either a customer's requirements for a chip, or a design specification for a partially manufactured semiconductor chip, the tools generate the RTL for control plane interconnect; memory composition, test, and manufacture; embedded logic analysis, trace interconnection, and utilization of spare resources on the chip; I/O qualification, JTAG, boundary scan, and SSO analysis; testable clock generation, control, and distribution; interconnection of all of the shared logic in a testable manner from a transistor fabric and/or configurable blocks in the slice. The input customer requirements are first conditioned by RTL analysis tools to quickly implement its logic. The slice definition and the RTL shell provides the correct logic for a set of logic interfaces for the design specification to connect. The tools share a common database so that logical interactions do not require multiple entries. The designs are qualified, tested, and verified by other tools. The tools further optimize the placement and timing of the blocks on the chip with respect to each other and with respect to placement on a board. The suite may be run as batch processes or can be driven interactively through a common graphical user interface. The tools also have an iterative mode and a global mode. In the iterative mode, one or more of the selected tools can generate the blocks or modify a design incrementally and then look at the consequences of the addition, or change. In the global mode, the semiconductor product is designed all at once in a batch process as above and then optimized altogether. This suite of generation tools generates design views including a qualified netlist for a foundry to manufacture.

7,043,703, Architecture and/or method for using input/output affinity region for flexible use of hard macro I/O buffers,
filed: September 11, 2002, issued: May 9, 2006
Inventors: George W. Nation, Gary S. Delp
An apparatus comprising (i) one or more input/output cells, (ii) one or more hard macros and (iii) one or more input/output affinity regions. The one or more input/output affinity regions may be disposed between the one or more input/output cells and the one or more hard macros. Each of the one or more input/output affinity regions may be customized as (i) circuitry in a first mode and (ii) routing between the one or more input/output cells and the one or more hard macros in a second mode.

7,043,611, Reconfigurable memory controller,
filed: December 11, 2002, issued: May 9, 2006
Inventors: Gary P. McClannahan, Gary S. Delp, George W. Nation
A reconfigurable memory controller includes a plurality of communicatively coupled memory controllers. The plurality of memory controllers may be configured into a first configuration based on a grouping of memory controllers and then reconfigured into a second configuration based on a different grouping of memory controllers, where the first and second configurations have different performance bandwidths for accessing memory.

6,966,044, Method for composing memory on programmable platform devices to meet varied memory requirements with a fixed set of resources,
filed: December 9, 2002, issued: November 15, 2005
Inventors: Paul G. Reuland, George W. Nation, Jonathan Byrn, Gary S. Delp
A method for composing memory on a programmable platform device comprising the steps of: (A) accepting information about a programmable platform device comprising one or more diffused memory regions and one or more gate array regions; (B) accepting predetermined design information for one or more memories; and (C) composing one or more memory building blocks (i) in the one or more diffused memory regions, (ii) in the one or more gate array regions or (iii) in both the diffused memory and the gate array regions based upon the predetermined design information and the information about the programmable platform device.

6,959,428, Designing and testing the interconnection of addressable devices of integrated circuits,
filed: June 19, 2003, issued: October 25, 2005
Inventors: Broberg, Robert Neal Carlton III, Troy Evan Faber, Gary Scott Delp, Paul Gary Reuland, Daniel James Murray
A register address generation tool is used during the design of semiconductor products. For those registers and/or memories that are addressable on a bus, the register address generation tool creates the interconnect RTL, header files, static timing analysis constraint files, and verification testcases. The tool also maintains coherence between what has been generated and the available resources for the design of the semiconductor product in a design. If there are any registers and/or memories that are not being used, the register address generation tool may further generate the RTL that will convert these unused resources to performance-enhancing features such as control registers, status registers, etc. The register address generation tool read a design database having an application set to determine what hardmacs and what transistor fabric is available. It also receives as input a bus specification and address parameters. The register address generation tool may be used with a suite of generation tools to achieve the rapid design and realization of a new semiconductor product.

6,823,502, Placement of configurable input/output buffer structures during design of integrated circuits,
filed: December 31, 2002, issued: November 23, 2004
Inventors: Matthew Scott Wingren, George Wayne Nation, Gary Scott Delp, Jonathan William Byrn
A tool for designing an integrated circuit and semiconductor product that generates correct RTL for I/O buffer structures in consideration of the requirements of diffused configurable I/O blocks and/or I/O hardmacs of the product. Given either a slice description of a partially manufactured semiconductor product, a designer can generate the I/O resources of an application set. Then given an application set having a transistor fabric, and the diffused configurable I/O blocks and/or the I/O hardmacs, and a plurality of accompanying shells, the I/O generation tool herein automatically reads a database having the slice description and generates the I/O buffer structures from the transistor fabric. The I/O generation tool further conditions and integrates input from either or both customer having her/his own logic and requesting a specific semiconductor product or from IP cores with their preestablished logic. The I/O generation tool creates correct RTL from the transistor fabric for correct placement, timing, testing, and function of I/O buffer amplifiers for the semiconductor product, either incrementally or globally. Once I/O buffer structures are created, they are qualified by a plurality of shells including a verification shell, a static timing analysis shell, a manufacturing test shell, and a RTL analysis shell.

6,823,499, Method for designing application specific integrated circuit structure,
filed: September 16, 2002, issued: November 23, 2004
Inventors: Ronnie Vasishta, Gary Delp
A method for designing an Application Specific Integrated Circuit (ASIC) structure on a semiconductor substrate, includes (a) defining a class of circuit designs, the class having a common design part shared within the class and a custom design part variable for individual designs in the class, (b) allocating a set of bottom layers and a set of top metal layers to implement the common design part, the allocated sets of bottom layers and top metal layers having a fixed pattern for the class, and (c) implementing the custom design part using metal layers above the allocated set of bottom layers and below the allocated set of top metal layers. The method may further includes characterizing the ASIC for the common design and using the fixed patterns of the allocated set of bottom layers and the allocated set of top metal layers.

6,765,911, Communications adapter for implementing communications in a network and providing multiple modes of communications,
filed: February 3, 1999, issued: July 20, 2004
Inventors: Mark William Branstad, Jonathan William Byrn, Gary Scott Delp, Philip Lynn Leichty, Todd Edwin Leonard, Gary Paul McClannahan, John Emery Nordman, Kevin Gerard Plotz, John Handley Shaffer, Albert Alfonse Slane
A method and apparatus are provided for implementing communications in a communications network. The apparatus for implementing communications includes a system interface to the communications network. A scheduler schedules enqueued cells and enqueued frames to be transmitted. A segmenter segments frames and cells in into cells or frames applied to a media adaptation block for transmission in a selected one of multiple modes.

6,667,978, Apparatus and method for reassembling frame data into stream data,
filed: July 9, 1998, issued: December 23, 2003
Inventors: Gary Scott Delp, Albert Alfonse Slane
The present invention is a method and apparatus for reducing processing overhead using a stream data reassembly mechanism and at least one data buffer. The present invention pre-processes incoming frames before delivering the frames to system memory. When a first packet of an data stream is received, the data from the packet is placed into a data buffer. Information about the first packet is stored in a logical channel descriptor (LCD) to indicate that data exists in the current data buffer. As each subsequent packet in the data stream is received, the reassembly mechanism removes extraneous transmission data from the packet and checks the CRC of each trailer to qualify the data within the packet. After the data is qualified, the reassembly mechanism stores the data portion of the packet in the data buffer. This preprocessing of each packet continues until a predetermined condition is met. Once a predetermined condition is met, the reassembly mechanism will make the contents of the buffer available to the system. The reassembly may optionally associate a direct memory access (DMA) descriptor with the buffer and burst the contents of the buffer into system memory. The reassembly mechanism of the present invention thereby reduces the amount of data reception interrupts processed by the system and can also reduce the number of direct memory access data transfer across the system bus.

6,601,200, Integrated circuit with a VLSI chip control and monitor interface, and apparatus and method for performing operations on an integrated circuit using the same,
filed: November 24, 1999, issued: July 29, 2003
Inventors: Gary Scott Delp, Antonius Paulus Engbersen, Andreas G. Herkersdorf
An integrated circuit (i.e., chip under test) includes a control and monitor interface that includes on-chip support for one or more network protocols that allow the chip to be directly coupled to a network. The control and monitor interface defines one or more operations that can be performed on the chip. In a system for testing chips under test, the control and monitor interface of all of the chips under test are coupled to a network, which is also coupled to a control and monitor mechanism. When a chip under test receives a message on the network from the control and monitor mechanism to execute an operation, it performs the requested operation, then reports the results. In this manner much of the intelligence regarding the test can be pushed on-chip, rather than having all of the testing intelligence residing in an external tester. This allows some standardization in tests that are performed from one chip under test to the next.

6,498,782, Communications methods and gigabit ethernet communications adapter providing quality of service and receiver connection speed differentiation,
filed: February 3, 1999, issued: December 24, 2002
Inventors: Mark William Branstad, Jonathan William Byrn, Gary Scott Delp, Philip Lynn Leichty, Todd Edwin Leonard, Gary Paul McClannahan, John Emery Nordman, Kevin Gerard Plotz, John Handley Shaffer, Albert Alfonse Slane
A method and Gigabit Ethernet communications adapter are provided for implementing communications in a communications network. A transmission queue is defined of data to be transmitted. A transmission rate is set for the transmission queue. Data to be transmitted are enqueued on the transmission queue. The transmission queue can be subdivided into multiple priority queues, for example, using time wheels, and a transmission rate is set for each transmission queue.

6,477,168, Cell/frame scheduling method and communications cell/frame scheduler,
filed: February 3, 1999, issued: November 5, 2002
Inventors: Gary Scott Delp, Philip Lynn Leichty, Kevin Gerard Plotz
A method and apparatus are provided for scheduling the transmission of cells and frames in a communications network. The transmission of cells and frames are scheduled utilizing a selected scheduling algorithm. The cell/frame scheduling algorithm includes the step of identifying a frame or cell transmission type. Responsive to the identified frame or cell transmission type, a frame multiplier value is identified. A target transmission time is calculated for the frame or cell transmission type utilizing the identified frame multiplier value. A method and apparatus optionally are provided for scheduling the transmission of packet pairs.

6,453,434, Dynamically-tunable memory controller,
filed: August 23, 2001, issued: September 17, 2002
Inventors: Gary Scott Delp, Gary Paul McClannahan
A memory controller circuit arrangement and method utilize a tuning circuit that dynamically controls the timing of memory control operations, rather than simply relying on fixed timing parameters that are either hardwired or initialized upon startup of a memory controller. Dynamic control over the timing of memory control operations typically incorporates memory test control logic that verifies whether or not a memory storage device will reliably operate using the dynamically-selected values of given timing parameters. Then, based upon the results of such testing, such dynamically-selected values are selectively updated and retested until optimum values are found. The dynamically-selected values may be used to set one or more programmable registers, each of which may in turn be used to control the operation of a programmable delay counter that enables a state transition in a state machine logic circuit to initiate performance of a memory control operation by the logic circuit. Dynamic tuning may also utilize a unique binary search engine circuit arrangement that updates one of two registers with an average of the current values stored in such registers based upon the result of a test performed using that average value. By selectively updating such registers, a fast convergence to an optimum value occurs with minimal circuitry.

6,334,174, Dynamically-tunable memory controller,
filed: February 10, 1999, issued: December 25, 2001
Inventors: Gary Scott Delp, Gary Paul McClannahan
A memory controller circuit arrangement and method utilize a tuning circuit that dynamically controls the timing of memory control operations, rather than simply relying on fixed timing parameters that are either hardwired or initialized upon startup of a memory controller. Dynamic control over the timing of memory control operations typically incorporates memory test control logic that verifies whether or not a memory storage device will reliably operate using the dynamically-selected values of given timing parameters. Then, based upon the results of such testing, such dynamically-selected values are selectively updated and retested until optimum values are found. The dynamically-selected values may be used to set one or more programmable registers, each of which may in turn be used to control the operation of a programmable delay counter that enables a state transition in a state machine logic circuit to initiate performance of a memory control operation by the logic circuit. Dynamic tuning may also utilize a unique binary search engine circuit arrangement that updates one of two registers with an average of the current values stored in such registers based upon the result of a test performed using that average value. By selectively updating such registers, a fast convergence to an optimum value occurs with minimal circuitry.

6,181,705, System and method for management a communications buffer,
filed: August 14, 1996, issued: January 30, 2001
Inventors: Mark William Branstad, Brad Louis Brech, Jonathan William Byrn, Gary Scott Delp, Rafael M. Montalvo
A network buffer memory is divided into pools of locations including a plurality of tinygram contiguous sections and a plurality of jumbogram contiguous sections. The tinygram contiguous sections available for storage of packets are listed in a list of tinygram pointers. The jumbogram contiguous sections available for storage of packets are also listed in a list of jumbogram pointers. A threshold for distinguishing the packets as tinygrams and jumbograms is programmed. As packets are received, they are measured against the threshold. Responsive to detection of an end of packet condition prior to reaching the threshold, storing the packet in a tinygram contiguous section. Otherwise, the packet is stored in a jumbogram contiguous section. Availability of sections is determined by query to the FIFO lists of pointers.

6,067,303, Method and apparatus for detecting and controlling data stream splicing in ATM networks,
filed: February 25, 1997, issued: May 23, 2000
Inventors: Kenneth Dale Aaker, Gary Scott Delp, David Richard Poulter, Albert Alfonse Slane
A method and apparatus are provided for detecting and controlling data stream splicing in a stream of multimedia digital data over a distribution communications network. Sequential transport stream packets are obtained. Predetermined fields of each transport stream packet are interrogated to identify a splice in the data stream. A predetermined task is initiated responsive to an identified splice. In accordance with feature of the invention, one predetermined task initiated responsive to the identified splice includes masking the interrogated predetermined fields to mask the splice in the data stream.

6,028,843, Earliest deadline first communications cell scheduler and scheduling method for transmitting earliest deadline cells first,
filed: March 25, 1997, issued: February 22, 2000
Inventors: Gary Scott Delp, Victor Firoiu, Roch A. Guerin, Philip Lynn Leichty, David Richard Poulter, Vinod Gerard John Peris, Rajendran Rajan, John Handley Shaffer
A method and apparatus are provided for scheduling the transmission of cells of a plurality of data streams in a communications network. An earliest deadline first (EDF) scheduler is provided for scheduling the transmission of cells of a plurality of data streams in a communications network to ensure that the connection or data stream with the earliest deadline is transmitted first. Each of the multiple data streams has a delay bound or deadline. Data of each data stream is enqueued to a corresponding data cell queue. A timing wheel time slot based on an identified target transmission time for each data cell queue is calculated utilizing an addition of a maximum delay value. A move forward timing mechanism includes a scan forward feature to identify a succession of virtual connection or data stream cell queues for transmission. A multiple tier cell scheduler is provided that includes at least two scheduling timing wheels. The priority of a first timing wheel is higher than the priority of a second timing wheel. The priority of the second timing wheel is higher than the priority of an optional third timing wheel. The third timing wheel includes a best effort operational mode. The relative rates between data streams are maintained, while the absolute rates of the data streams are increased or decreased in the lowest priority wheel.

5,996,013, Method and apparatus for resource allocation with guarantees,
filed: April 30, 1997, issued: November 30, 1999
Inventors: Gary Scott Delp, Roch A. Guerin, Philip Lynn Leichty, Vinod Gerard John Peris, Rajendran Rajan, Albert Alfonse Slane
A method and apparatus are provided for resource allocation with guarantees. A resource allocator is coupled to a controller. The resource allocator allocates resources between a plurality of arrival processes. A dedicated resource pool and a shared resource pool are provided. When an arrival process is identified, the resource allocator obtains a predefined characterizing value for the identified arrival process. Responsive to the obtained predefined characterizing value, resource from one of the dedicated resource pool or the shared resource pool is allocated to the arrival process. The controller is utilized for tracking resource use and for providing the predefined characterizing value for each of the plurality of arrival processes. The dedicated resource pool has a predetermined capacity greater than or equal to the total of all the low threshold values for each of the arrival processes. The dedicated resource pool provides the guarantees with the shared pool providing statistical multiplexed resource use. The controller increments a usage charge for the arrival process when a resource is allocated and decrements the usage charge at the end of use of the allocated resource. The controller evaluates use for the identified arrival process and updates the predefined characterizing value.

5,940,404, Method and apparatus for enhanced scatter mode allowing user data to be page aligned,
filed: April 30, 1997, issued: August 17, 1999
Inventors: Gary Scott Delp, Albert Alfonse Slane
A method and apparatus are provided for enhanced scatter mode allowing user data to be page aligned in a memory. An adapter is coupled between a data communications network and the memory. A data packet including protocol header bytes is received from a data communications network by the adapter. A variable amount of data is specified for a first scatter page that contains the protocol header bytes. Subsequent sequential pages from the received data packet are transferred, for example, by direct memory access (DMA) operations, to real page addresses in the memory with the sequential pages transferred being page aligned in the memory. A page address is written to a DMA list stored in an adapter memory for the sequential pages transferred. A count value is incremented in a packet header of a number of pages transferred for each sequential page transferred. Responsive to transferring a last page from the received data packet, the first scatter page containing the packet header, the DMA list and the protocol header bytes is transferred to a separate address space in the memory. A small packet or single page size is specified for the adapter. When the total data size of a received packet is less than this small packet size, then the packet is not scattered. A single page mode is performed to transfer the small packet to the memory.

5,930,252, Method and apparatus for queuing and triggering data flow streams for ATM networks,
filed: December 11, 1996, issued: July 27, 1999
Inventors: Kenneth Dale Aaker, Gary Scott Delp, Stephen Gouze Luning, Jeffrey James Lynch
An improved method and apparatus are provided for queuing and triggering the flow of data across ATM networks. A connection is established between an insertion server and a client multiplexer. The insertion server prepares a timing response and establishes a transmit queue threshold for a pending trigger point for inserting data. The insertion server enqueues data. Responsive to receiving a timing request from the client multiplexer, the insertion server sends the timing response. Responsive to receiving a stream request from the client multiplexer, the insertion server transfers the enqueued data. The client multiplexer includes a timer for identifying an offset time between sending the timing request and receiving a timing response from the insertion server. The client multiplexer uses the offset time to set a count down timer for sending the stream request. The client multiplexer processes the data transferred by the insertion server and optionally sends a stop stream command to the insertion server.

5,844,890, Communications cell scheduler and scheduling method for providing proportional use of network bandwith,
filed: March 25, 1997, issued: December 1, 1998
Inventors: Gary Scott Delp, Philip Lynn Leichty
A method and apparatus are provided for scheduling the transmission of cells of a plurality of data streams in a communications network. A best effort scheduler is provided for scheduling the transmission of cells of a plurality of data streams in a communications network. The best effort scheduler includes a best effort operational mode and can include more than one timing wheel. When the best effort scheduler includes more than one timing wheel, then the priority of the best effort timing wheel is lower than the priority of the other timing wheel or wheels. Data of each data stream is enqueued to a corresponding data cell queue. A target next transmission time for each data cell queue is calculated utilizing predetermined logical channel descriptor parameters. A lower priority or a higher priority timing wheel is selected and a timing wheel time slot is calculated based on an identified target transmission time for each active data cell queue. An active indication is set for the identified timing wheel time slot and an entry is stored to point to the corresponding data cell queue for the identified timing wheel time slot. The relative rates between data streams are maintained, while the absolute rates of the data streams are increased or decreased in the low priority wheel. Scheduling opportunities can be defined utilizing a predefined pseudo data cell queue. Then the calculation of the target transmission time for each data cell queue includes the predefined pseudo data cell queue, and the identified target transmission time for the predefined pseudo data cell queue defines scheduling opportunities of multiple timing wheel time slots.

5,815,516, Method and apparatus for producing transmission control protocol checksums using internet protocol fragmentation,
filed: April 5, 1996, issued: September 29, 1998
Inventors: Kenneth Dale Aaker, Gary Scott Delp, Lee Anton Sendelbach, Albert Alfonse Slane
An improved method and apparatus are provided for producing transmission control protocol (TCP) checksums using internet protocol (IP) fragmentation. A transmission control protocol module receives packet data to be transmitted and prepares a first internet protocol data fragment without a checksum for the received packet data. The first internet protocol data fragment is transmitted. Collecting checksum is performed during the transmission of the first internet protocol data fragment. Then an internet protocol header fragment including the collected checksum is transmitted.

5,781,763, Independent control of DMA and I/O resources for mixed-endian computing systems,
filed: May 22, 1997, issued: July 14, 1998
Inventors: Bruce Leroy Beukema, Gary Scott Delp, Larry Wayne Loen, Daniel Frank Moertl, Michael R. Trombley
A mixed-endian computer system enhanced to manage I/O DMA without a software DMA performance penalty. A mixed-endian computer system can change endian mode on a task by task basis if necessary. The mixed-endian system, as enhanced, performs one of two well-defined DMA operations based on control bits either in the DMA control register or in a bit vector associated with each page of processor storage. This invention also describes means for treating I/O registers as if they were of the endian of the executing processor, instead of the more typical need to have the register operate in a particular endian.

5,761,716, Rate based memory replacement mechanism for replacing cache entries when the cache is full,
filed: May 1, 1996, issued: June 2, 1998
Inventors: Jonathan William Byrn, Gary Scott Delp, Kevin Gerard Plotz
A rate based mechanism for determining which data to replace in a cache when the cache is full. The computer system processes data, which are associated with multiple channels or processes. These channels or processes have different, cyclic rates. When the cache is full, the system chooses the data to replace by selecting the data block in the cache that has the lowest rate and is the most recently used.

5,758,087, Apparatus and method for predicted response generation,
filed: June 14, 1996, issued: May 26, 1998
Inventors: Kenneth Dale Aaker, Gary Scott Delp, Brad Louis Brech
A method and apparatus are provided for generation of predicted responses in a computer communications network system. A server in the computer communications network system predicts the client's next request based on the present client's request. The server sets a trigger that recognizes a match of the client's predicted request. When a client's predicted request arrives, the trigger sends the response. Additionally, the server associates a timeout action with the predicted response so that if a predicted request is not received within the timeout interval or other events occur before the predicted request arrives, the triggered response is removed and an alternative action is performed.

5,754,768, System for selectively and cumulatively grouping packets from different sessions upon the absence of exception condition and sending the packets after preselected time conditions,
filed: July 23, 1996, issued: May 19, 1998
Inventors: Brad Louis Brech, Gary Scott Delp, Albert Alfonse Slane
A method and apparatus processing system for enhancing the processing of a plurality of related packets received at a logical unit within a data processing system are disclosed. A plurality of packets are received at the logical unit. Then each of the plurality of packets are examined and a session identification is obtained for each of the plurality of packets. During a preselected time window, each of the plurality of packets are associated with a group. Each packet in a group has a session identification that is identical to every other packet within the group.

5,752,078, System for minimizing latency data reception and handling data packet error if detected while transferring data packet from adapter memory to host memory,
filed: July 10, 1995, issued: May 12, 1998
Inventors: Gary S. Delp, Philip L. Leichty, Albert A. Slane
A method and system within a data processing system are disclosed for receiving information from a communications network. The data processing system includes a communications adapter, having an adapter memory, and a host memory. The communications adapter is coupled to the communications network, which transmits information to the data processing system in packets including a packet header and packet data. According to the present invention, a portion of a packet of information is received from the communications network at the adapter memory within the communications adapter. The portion of the packet of information includes at least a packet header that specifies a length of the packet of information and a destination address within the host memory. In response to receipt of the portion of the packet of information, a transfer of the packet of information from the adapter memory to the host memory is prepared prior to receipt of a final portion of the packet of information at the adapter memory. The packet of information is then transferred from the adapter memory to addresses within the host memory beginning with the destination address. Since the transfer is prepared before packet receipt is complete, perceived latency is minimized.

5,737,638, System for determining plurality of data transformations to be performed upon single set of data during single transfer by examining communication data structure,
filed: July 14, 1995, issued: April 7, 1998
Inventors: Jonathan W. Byrn, Gary S. Delp, Philip L. Leichty, Robert J. Manulik, Meyer, Arthur J. III, Albert A. Slane
A method and apparatus are disclosed for providing an inline data service within a data processing system coupled to a communications network. The data processing system includes a host memory. According to the present invention, the apparatus comprises an adapter memory for temporarily storing data communicated between the data processing system and the communications network and a memory access controller, which controls transfers of data between the adapter memory and the host memory. The apparatus further includes means for selectively performing a data transformation on data transferred between the adapter memory and the host memory, wherein the data transformation is performed during a transfer of the data such that data communication latency is reduced. In a second preferred embodiment of the present invention, a multibus data processing system has a processor and a first memory coupled to a first bus and a second memory coupled to a second bus. A bridge adapter, including means for transferring data from the first memory to the second memory and means for selectively performing a data transformation, is coupled between the first and second buses. During transfers of data from the first memory to the second memory, the bridge adapter selectively performs data transformations on the data, such that data processing latency is reduced.

5,721,874, Configurable cache with variable, dynamically addressable line sizes,
filed: June 16, 1995, issued: February 24, 1998
Inventors: Michael Joseph Carnevale, Gary Scott Delp
A configurable variable cache includes a cache memory for storing data. The cache memory is selectively configured into a variable number of variable size lines. At least one user is connected to the cache memory. An addressing function coupled to the cache memory is used for accessing the lines of the cache.

5,706,461, Method and apparatus for implementing virtual memory having multiple selected page sizes,
filed: April 26, 1996, issued: January 6, 1998
Inventors: Mark William Branstad, Jonathan William Byrn, Gary Scott Delp, Philip Lynn Leichty, Kevin Gerard Plotz, Fadi-Christian E. Safi, Albert Alfonse Slane
A method and apparatus for implementing virtual memory having multiple selected page sizes are provided. A virtual address includes a map index and a frame offset. A selector mechanism receives the virtual address frame offset and generates an offset and index. A frame map table indexes the virtual address map index and the selector generated index and generates a base address. The frame map table generated base address and the selector generated offset are combined to provide a physical address.

5,652,749, Apparatus and method for segmentation and time synchronization of the transmission of a multiple program multimedia data stream,
filed: July 25, 1996, issued: July 29, 1997
Inventors: David William Davenport, Gary Scott Delp, Jeffrey James Lynch, Kevin G. Plotz, Philip Lynn Leichty
Method and apparatus are provided for segmenting a multiple program multimedia digital data stream for transmission over a distribution communications network. Each program multimedia digital data stream includes sequential transport system (TS) packets with program clock references (PCRs) at a set time interval and a program identification (PID) associated with the PCRs. The multiple program multimedia digital data stream is received. The TS packets are decoded to identify the program clock references (PCRs). A selected number N of TS packets are identified. The multimedia digital data stream into frames responsive to both the identified number N of TS packets and the identified PCRs. A program identification (PID) associated with one of the PCRs is selected for timing the transmission of segmented multiple program multimedia digital data stream. A time interval following an identified PCR associated with the selected program identification PID is identified and compared with the set time interval between the program clock references (PCRs). Responsive to the identified time interval being greater than the set time interval, a new program identification (PID) is selected for timing the transmission of segmented multiple program multimedia digital data stream.

5,634,015, Generic high bandwidth adapter providing data communications between diverse communication networks and computer system,
filed: October 4, 1994, issued: May 27, 1997
Inventors: Paul Chang, Gary S. Delp, Hanafy E.-S. Meleis, Rafael M. Montalvo, David I. Seidman, Ahmed N.-E.-D. Tantawy, Dominick A. Zumbo
A generic high bandwidth adapter providing a unified architecture for data communications between buses, channels, processors, switch fabrics and/or communication networks. Data is carried by data stream packets of variable lengths, and each packet includes a header control information portion required by communication protocols used to mediate the information exchange, and normally a data portion for the data which is to be communicated. A packet memory stores data packets arriving at a plurality of generic adapter input/output ports. The packet memory is segmented into a plurality of buffers, and each data packet is stored in one or more buffers as required by the length thereof. A generic adapter manager is provided for performing and synchronizing generic adapter management functions, including implementing data structures in the packet memory by organizing data packets in buffers, and organizing data packets into queues for processing by the processor subsystem or transfer to or from generic adapter input/output ports. The generic adapter manager prepares future response to anticipated requests for communications services which are functions of the current requests for communication services, such as preparing a response for an anticipated request for a next buffer by a current request for a receipt of data. The generic adapter manager stores the future responses at specified addresses in memory which can be read by a requester. Each generic adapter input/output port has associated therewith a packet memory interface providing for the transfer of data packets into and out of the packet memory, such that when a data packet is received at an input/output port, the data packet is transferred into the adapter packet memory and queued for processing.

5,629,933, Method and system for enhanced communication in a multisession packet based communication system,
filed: June 7, 1995, issued: May 13, 1997
Inventors: Gary S. Delp, Albert A. Slane
The method and system for enhanced efficiency in a multisession communication system which utilizes a series of data packets wherein each data packet includes an indication of the identity of a particular session to which that data packet belongs. Each received data packet is examined as that data packet is received to determine a session identity for that packet. An indication of the session identity is thereafter listed within a session queue only in response to an initial occurrence of that session identity. Each data packet for a listed session identity is then stored in a data packet queue in First-In First-Out (FIFO) order which is associated with the listed session identity wherein all packets for a session remain in order, even though the overall order of all packets may be enhanced. In this manner all data packets within a particular session may be efficiently accessed for processing or, alternatively, one or more data packets within each session may be accessed serially for processing in a round-robin fashion.

5,598,535, System for selectively and cumulatively grouping packets from different sessions upon the absence of exception condition and sending the packets after preselected time conditions,
filed: August 1, 1994, issued: January 28, 1997
Inventors: Brad L. Brech, Gary S. Delp, Albert A. Slane
The present invention provides a method and apparatus processing system for enhancing the processing of a plurality of related packets received at a logical unit within a data processing system. A plurality of packets are received at the logical unit. Then each of the plurality of packets are examined and a session identification is obtained for each of the plurality of packets. During a preselected time window, each of the plurality of packets are associated with a group. Each packet in a group has a session identification that is identical to every other packet within the group.

5,555,387, Method and apparatus for implementing virtual memory having multiple selected page sizes,
filed: June 6, 1995, issued: September 10, 1996
Inventors: Mark W. Branstad, Jonathan W. Byrn, Gary S. Delp, Philip L. Leichty, Kevin G. Plotz, Fadi-Christian E. Safi, Albert A. Slane
A method and apparatus for implementing virtual memory having multiple selected page sizes are provided. A virtual address includes a map index and a frame offset. A selector mechanism receives the virtual address frame offset and generates an offset and index. A frame map table indexes the virtual address map index and the selector generated index and generates a base address. The frame map table generated base address and the selector generated offset are combined to provide a physical address.

5,537,408, apparatus and method for segmentation and time synchronization of the transmission of multimedia data,
filed: June 5, 1995, issued: July 16, 1996
Inventors: Mark W. Branstad, Jonathan W. Byrn, Gary S. Delp, Phillip L. Leichty, Jeffrey J. Lynch, Kevin G. Plotz, Lee A. Sendelbach, Albert A. Slane
Method and apparatus are provided for transmitting a stream of multimedia digital data over a distribution communications network. A multimedia stream server segments the multimedia digital data stream into data blocks on a first boundary and a second boundary. The first boundary is a set number of transport system data packets and the second boundary is a transport system data packet including a timestamp. A scheduler schedules the segmented data blocks for transmission. The multimedia stream server decodes the segmented data blocks to locate the timestamps and matches the transmission of the located timestamp data block with a time value indicated by the timestamp. The set number of transport system data packets can be determined at connection setup and is not a predetermined value for all sessions. At the receiver, batch processing of received multimedia data can be provided.

5,533,021, Apparatus and method for segmentation and time synchronization of the transmission of multimedia data,
filed: February 3, 1995, issued: July 2, 1996
Inventors: Mark W. Branstad, Jonathan W. Byrn, Gary S. Delp, Philip L. Leichty, Jeffrey J. Lynch, Kevin G. Plotz, Lee A. Sendelbach, Albert A. Slane
Method and apparatus are provided for transmitting a stream of multimedia digital data over a distribution communications network. A multimedia stream server segments the multimedia digital data stream into data blocks on a first boundary and a second boundary. The first boundary is a set number of transport system data packets and the second boundary is a transport system data packet including a timestamp. A scheduler schedules the segmented data blocks for transmission. The multimedia stream server decodes the segmented data blocks to locate the timestamps and matches the transmission of the located timestamp data block with a time value indicated by the timestamp. The set number of transport system data packets can be determined at connection setup and is not a predetermined value for all sessions. At the receiver, batch processing of received multimedia data can be provided.

5,533,020, ATM cell scheduler,
filed: October 31, 1994, issued: July 2, 1996
Inventors: Jonathan W. Byrn, Gary S. Delp, Philip L. Leichty, Baiju V. Patel, Kevin G. Plotz, Frank A. Schaffa, Marc H. Willebeek-LeMair
A method and apparatus for scheduling the transmission of a number of data streams over a common communications link, where each of the data streams conforms to a corresponding set of flow control parameters. Each of the data streams to be transmitted on the communications link is stored in a corresponding queue. The status of each queue is maintained, and a target transmission time is calculated for each queue. Signals are then generated for each queue at a time at least after the target transmission time, and these signals are used to indicate to a corresponding queue that is can transmit a cell on the link. Upon reception of a corresponding signal, a queue then transmits at least one cell onto the communications link.

5,502,833, System and method for management of a predictive split cache for supporting FIFO queues,
filed: March 30, 1994, issued: March 26, 1996
Inventors: Jonathan W. Byrn, Gary S. Delp
A first-in, first-out queue is implemented on two memory elements by enqueuing and dequeuing items from a first memory element and by swapping middle portions of the queue between the first memory element and the second memory whenever the first memory element is sufficiently filled. Where the second element is system memory for a computer system, queue length can be allowed to grow almost arbitrarily while preserving the performance of first memory element.

5,367,643, Generic high bandwidth adapter having data packet memory configured in three level hierarchy for temporary storage of variable length data packets,
filed: February 6, 1991, issued: November 22, 1994
Inventors: Paul Chang, Gary S. Delp, Hanafy E. Meleis, Rafael M. Montalvo, David I. Seidman, Ahmed N. Tantawy, Dominick A. Zumbo
A generic high bandwidth adapter providing a unified architecture for data communications between buses, channels, processors, switch fabrics and/or communication networks. Data is carried by data stream packets of variable lengths, and each packet includes a header control information portion required by communication protocols used to mediate the information exchange, and normally a data portion for the data which is to be communicated. The generic high bandwidth adapter comprises a processor subsystem including a processor for processing the header control information portions of data packets. The processor has access to data packets stored in a packet memory which stores data packets arriving at four generic adapter input/output ports. The packet memory is segmented into a plurality of buffers, and each data packet is stored in one or more buffers as required by the length thereof. A generic adapter manager is provided for performing and synchronizing generic adapter management functions, including implementing data structures in the packet memory by organizing data packets in buffers, and organizing data packets into queues for processing by the processor subsystem or transfer to or from generic adapter input/output ports. Each generic adapter input/output port has associated therewith a packet memory interface providing for the transfer of data packets into and out of the packet memory, such that when a data packet is received at an input/output port, the data packet is transferred into the adapter packet memory and queued for processing.

5,287,527, Logical signal output drivers for integrated circuit interconnection,
filed: December 28, 1992, issued: February 15, 1994
Inventors: Gary S. Delp, Brian A. Schuelke
Disclosed is a logic output signal generating integrated circuit having a plurality of output drivers connected in parallel between a power bus and a ground bus. Each output driver has a pull up device disposed between the power bus and an output terminal and a pull down device disposed between the output terminal and the ground bus. Output drivers are paired for the reception of control signals. Control gates to the pull up device and the pull down device for one output driver in a pair is connected to receive an on-chip logic signal. The second output driver of the pair has the complement of that logic signal applied to the control gates of its pull up and pull down devices. An inverter operates on the logic signal to provide the complement. The load is divided between the output drivers for the true signals and those for the complementary signals.

5,260,942, Method and apparatus for batching the receipt of data packets,
filed: March 6, 1992, issued: November 9, 1993
Inventors: Richard A. Auerbach, Jerry A. Blades, Jonathan W. Byrn, Gary S. Delp
A method and a system in a distributed data processing network for enhancing the processing of a plurality of related data packets received at a receiving station within the distributed data processing network, each of the data packets having a header associated herewith includes sequentially receiving a number of data packets at the receiving station. Next, the header associated with a first data packet is examined and predicted profile is generated for comparison with a related subsequent data packet. The next data packet received is then compared with the predicted profile to determine whether or not the two data packets may be consolidated.